1. Field of the Invention
The embodiments herein generally relate to integrated circuit chips and more particularly to an integrated circuit chip having an enhanced programming and test interface and an associated method of monitoring, healing and testing the chip using the enhanced programming and test interface.
2. Description of Related Art
Nanoscale integrated circuit (IC) devices are prone to significant variation in threshold voltage caused by intrinsic aspects such as line-edge roughness, random dopant fluctuations, and body thickness variations in silicon-on-insulator devices. Such variation can lead to significant spreads in circuit delay, power, and robustness for digital ICs, and performance for analogs ICs.
Furthermore, the growing complexity of system hardware is defeating the enormous effort put forth by verification engineers to ensure system correctness. The reason is that verification is unable to keep up with modern high-productivity design solutions such as high-performance application specific integrated circuits (ASICs) and systems-on-a-chip (SoCs), which feature multiple complex hardware and software components connected by diverse sets of interfaces. Today, most, if not all, complex system designs are released containing latent bugs, which sometimes become evident only after a design reaches the market.
Ultimately, these challenges threaten the continued scaling of silicon fabrication technologies. A primary goal of transistor scaling is to reduce the cost of electronic devices. As devices scale to smaller geometries, however, they become less reliable, necessitating the inclusion of design for reliability features.
Reliability costs range from service and replacement to built-in solutions entailing area and design resources. These costs are increasing at technology nodes with higher natural failure rates, which require more robust and finer-grained reliability techniques.